TSMC is accelerating its push into co-packaged optics as rising GPU and ASIC computing power pushes traditional copper interconnects toward limits in power consumption and signal transmission, Taiwan's Commercial Times reported on September 14. According to ChainCatcher, industry analysts said CPO bandwidth could double every two years, potentially creating an AI-era "CPO Moore's Law."
Analysts said CPO bandwidth upgrades are expected to follow three main paths: single-channel speeds rising from 200G to above 400G, optical channel counts expanding from 16 to 32 and beyond 64, and the adoption of wavelength division multiplexing. By 2040, theoretical bandwidth could reach about 128 times current levels, with long-term room to grow into the hundreds of terabits.
TSMC's role in optical interconnects is expanding from foundry services to system integration, spanning 3DFabric, CoWoS, SoIC, silicon photonics, and CPO. The company is integrating compute, HBM memory, and high-speed I/O as the industry shortens copper paths and extends optical paths after high-speed electrical signals exceed 200G and weaken across ABF substrates, PCBs, and connectors.
In packaging, optical engines are currently being placed on substrates, with CPO expected next on interposers and, later, PICs and ASICs potentially moving toward 3D vertical integration through SoIC technology. Industry participants said mass production of CPO still needs to overcome packaging, optical coupling, and testing challenges.