SK Hynix Says Next-Generation 3D DRAM Can Use Foundry Processes

SK Hynix said on the 9th that development of next-generation 3D DRAM semiconductors can use foundry processes. According to ChainCatcher, the company outlined key technical directions for 3D DRAM at its 2026 SK Hynix Future Forum held the previous day at the Supex Center in its Icheon campus. Vice Presidents Kim Kyung-hoon and Son Ho-young said the main priorities include using logic foundry processes for DRAM peripheral circuits, maximizing data bus bandwidth, and enabling ultra-short-distance transmission. They said 3D DRAM vertically stacks memory cells that were previously laid out on a flat plane to improve integration. They added that, beyond design and heat issues, the technology also requires solutions for fine interconnects, bonding, and process integration in packaging. As the boundaries between front-end and back-end packaging and between foundry and memory technologies narrow, they said joint optimization across existing fields will become more important. Son said 3D technology is changing the technical boundary between wafer fabs and packaging, and that new optimization and collaboration systems beyond existing fields are needed alongside advanced packaging innovation. Korea University professor Shin Chang-hwan said 3D DRAM is not only about vertically stacking chips, but also about breaking the boundary between memory and logic. He said a shift to 3D technology is inevitable as device miniaturization approaches its limit and data movement between systems and memory increases time and power consumption, and proposed an AI-linked 3D integrated design framework spanning materials, devices, packaging, and architecture. In remarks at the forum, SK Hynix President Kwak Noh-jung said the memory market used to resemble a straight road where companies competed to run faster, but now it is like a constantly changing curve, making it important to adapt flexibly to external changes in speed and direction as well as internal capabilities.