Samsung Electro-Mechanics Executive Outlines MLC Direction for AI Semiconductor Substrates

Samsung Electro-Mechanics packaging division manager Kim Sang-hoon spoke at the KPCA Show INSIGHT 2026 international seminar in Incheon on September 10, outlining multilayer core technology as a response to larger and more highly layered AI semiconductor packaging substrates. According to ChainCatcher, he said the shift from single-layer core structures to multilayer combinations of CCL and PPG, or even hybrid structures using two CCL layers, can improve rigidity and routing flexibility while allowing ground or signal traces to be placed in PPG layers. Kim said the traditional approach of increasing the thickness of a single CCL makes internal via and circuit processing more difficult as the core thickens, while via size becomes more constrained. He added that adding a bonding layer between two CCLs can provide more stable substrate support, but the process is more complex. He also said current mass production commonly uses bump pitches above 90 μm, while around 85 μm marks the turning point for printed fine solder ball processes. Difficulty rises sharply near 80 μm, and the 55–45 μm range may shift toward metal bumps. Kim said glass cores offer higher rigidity and lower thermal expansion, which can help reduce warpage in large packages, but brittle handling and microvia plating still need to be solved. He added that substrates must meet signal integrity, power integrity, and mechanical integrity requirements, and that high-performance packaging substrates are expected to evolve from about 20 layers and 90 mm scale toward 120 mm scale and more than 40 layers.