TSMC Expected to Keep Using Microbumps for HBM Packaging in the Near Term

TSMC is expected to continue using conventional microbump technology rather than hybrid bonding for advanced packaging that connects high-bandwidth memory, or HBM, with AI accelerators, according to materials industry sources cited on September 2. According to ChainCatcher, finer-pitch microbumps are expected to remain in use through the later stage of HBM4 and the early stage of HBM5. TSMC has asked materials and equipment partners to develop bonding and underfill solutions for bumps of about 5 microns, with suppliers in South Korea and Japan already working on the effort. Mass production of 5-micron bumps is expected to begin in the second half of 2028. Current HBM3E bumps are about 15 to 25 microns high, while HBM4 is close to 10 microns. Japanese materials suppliers had previously said it was difficult to guarantee quality below 15 microns. The smaller bump size is intended to address HBM stack height limits and the need for higher interconnect density. JEDEC sets the maximum HBM stack height at 775 microns. In TSMC's advanced CoWoS packaging, HBM stacks assembled by GPU and memory suppliers are mounted onto a silicon interposer through microbumps, while 16-layer DRAM die stacks are completed inside HBM packages by companies including SK hynix and Samsung Electronics. Hybrid bonding, which directly bonds copper pads to enable thinner and denser interconnects, is already used by TSMC on its SoIC platform for logic chip stacking, but HBM still relies on microbumps to connect to the interposer.