AMD unveiled its sixth-generation EPYC 9006 series server CPU, code-named Venice, and its next-generation Instinct MI455X AI accelerator on July 23 at its annual Advancing AI event, according to Jiemian News. Venice uses TSMC’s 2nm process, while MI455X combines 2nm compute chiplets with 3nm I/O and cache chiplets. The report said Apple is still expected to use TSMC’s first-generation 2nm N2 process in the iPhone 18 Pro series later this year, but AMD was first to put 2nm into marketable chips.
Venice is said to pack up to 256 CPU cores, 512 threads, 16-channel DDR5 memory, up to 12,800MT/s MRDIMM support and PCIe 6.0. AMD positioned it not only for traditional cloud servers but also for AI host nodes and agent workloads. MI455X is described as a 320 billion-transistor chip with 432GB of HBM4 and peak memory bandwidth of 23.3TB/s. AMD also said 72 MI455X accelerators, Venice CPUs, Pensando networking chips and ROCm software can be combined into a Helios rack designed to compete with Nvidia’s Vera Rubin NVL72.
The article said the shift in first use of the most advanced process reflects how AI and data centers have overtaken smartphones as the main demand driver for leading-edge semiconductors. TSMC has said N2 can deliver 10% to 15% better performance at the same power, or cut power consumption by 25% to 30% at the same performance versus N3E. The report added that TSMC’s second-quarter HPC business accounted for 66% of revenue, while smartphones made up 22%, and 2nm already contributed 3% of wafer revenue.
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